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SSM4501GSD N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET PRODUCT SUMMARY D2 D2 D1 D1 N-CH BVDSS RDS(ON) ID G2 30V 27m 7A -30V 49m -5A Simple Drive Requirement Low On-resistance Fast Switching Characteristic P-CH BVDSS RDS(ON) ID PDIP-8 S2 G1 S1 DESCRIPTION The advanced power MOSFETs from Silicon Standard Corp. provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. D1 D2 G1 Pb-free; RoHS-compliant G2 S1 S2 ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID@TA=25 ID@TA=70 IDM PD@TA=25 TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating N-channel 30 20 7 5.8 40 2 0.016 -55 to 150 -55 to 150 P-channel -30 20 -5 -4.2 -30 Units V V A A A W W/ Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range THERMAL DATA Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 62.5 Unit /W 01/28/2008 Rev.1.00 www.SiliconStandard.com 1 SSM4501GSD N-CH ELECTRICAL CHARACTERISTICS @TJ=25 C (unless otherwise specified ) Symbol BVDSS BVDSS/Tj o Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance2 Test Conditions VGS=0V, ID=250uA Min. Typ. Max. Units 30 1 0.03 12 9 2 5 6 5 19 4 645 150 95 27 50 3 1 25 13 800 V V/ m m V S uA uA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25, ID=1mA RDS(ON) VGS=10V, ID=7A VGS=4.5V, ID=5A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=250uA VDS=10V, ID=7A VDS=30V, VGS=0V VDS=24V, VGS=0V VGS=20V ID=7A VDS=24V VGS=4.5V VDS=15V ID=1A RG=3.3,VGS=10V RD=15 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 100 nA Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 SOURCE-DRAIN DIODE Symbol VSD trr Qrr Parameter Forward On Voltage 2 2 Test Conditions IS=1.7A, VGS=0V IS=7A, VGS=0V, dI/dt=100A/s Min. Typ. Max. Units 16 10 1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge 01/28/2008 Rev.1.00 www.SiliconStandard.com 2 SSM4501GSD P-CH ELECTRICAL CHARACTERISTICS @TJ=25 C (unless otherwise specified ) Symbol BVDSS BVDSS/Tj o Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current ( T=25 C) j Drain-Source Leakage Current ( T=70 C) j o o Test Conditions VGS=0V, ID=-250uA 2 Min. Typ. Max. Units -30 -1 -0.03 8 9 2 5 10 7 27 16 180 130 49 75 -3 -1 -25 15 V V/ m m V S uA uA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25, ID=-1mA RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss VGS=-10V, ID=-5A VGS=-4.5V, ID=-3A VDS=VGS, ID=-250uA VDS=-10V, ID=-5.3A VDS=-30V, VGS=0V VDS=-24V, VGS=0V VGS= 20V ID=-5A VDS=-24V VGS=-4.5V VDS=-15V ID=-1A RG=6,VGS=-10V RD=15 VGS=0V VDS=-25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 100 nA Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 460 730 SOURCE-DRAIN DIODE Symbol VSD trr Qrr Parameter Forward On Voltage 2 2 Test Conditions IS=-1.7A, VGS=0V IS=-5A, VGS=0V, dI/dt=100A/s Min. Typ. Max. Units 21 18 -1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 2 3.Mounted on 1 in copper pad of FR4 board ; 90/W when mounted on Min. copper pad. 01/28/2008 Rev.1.00 www.SiliconStandard.com 3 SSM4501GSD N-Channel 40 36 T A =25 o C 30 ID , Drain Current (A) ID , Drain Current (A) 10V 8.0V 6.0V 5.0V T A =150 o C 10V 8.0V 6.0V 5.0V 24 20 12 V G =4. 0 V 10 V G =4.0V 0 0 1 2 3 4 0 0 2 3 5 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 2 I D =7A T A =25 Normalized RDS(ON) 70 1.4 I D =7A V G = 10V RDS(ON) (m ) 40 0.8 10 2 5 8 11 0.2 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 3 10 2.5 1 2 IS(A) T J =150 o C T J =25 C o VGS(th) (V) 1.2 1.5 0.1 1 0.5 0.01 0 0.4 0.8 0 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 01/28/2008 Rev.1.00 Fig 6. Gate Threshold Voltage v.s. Junction Temperature 4 www.SiliconStandard.com SSM4501GSD N-Channel f=1.0MHz 12 1000 I D =7.0A VGS , Gate to Source Voltage (V) 9 C iss V DS =16V V DS =20V V DS =24V C (pF) 100 6 C oss C rss 3 0 0 4 8 12 16 10 1 7 13 19 25 31 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 100us 10 Normalized Thermal Response (Rthja) Duty Factor = 0.5 0.2 1ms ID (A) 1 0.1 0.1 0.05 10ms 100ms 1s 10s DC 0.02 0.01 0.01 Single Pulse PDM t T 0.1 T A =25 C Single Pulse 0.01 0.1 1 10 o Duty Factor = t/T Peak Tj = PDM x Rthja + Ta Rthja =90o C/W 0.001 100 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off)tf Charge Q Fig 11. Switching Time Waveform 01/28/2008 Rev.1.00 Fig 12. Gate Charge Waveform 5 www.SiliconStandard.com SSM4501GSD P-Channel 40 36 T A =25 o C 30 -10V -8.0V -6.0V -ID , Drain Current (A) 24 T A =150 C o -10V -8.0V -6.0V -ID , Drain Current (A) -5.0V 20 -5.0V 12 10 V G = - 4. 0 V V G = - 4. 0 V 0 0 1 2 3 4 0 0 1 2 3 4 5 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 120 1.8 I D =-5.0A T A =25 Normalized R DS(ON) 1.6 I D =-5.0A V G = -10V 90 1.4 RDS(ON) (m ) 1.2 60 1 0.8 30 3 5 7 9 11 0.6 -50 0 50 100 150 -V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 3 10 2.5 1 2 -IS(A) T j =150 o C T j =25 o C -VGS(th) (V) 1.3 1.5 0.1 1 0.5 0.01 0.1 0.4 0.7 1 0 -50 0 50 100 150 -V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( C ) o Fig 5. Forward Characteristic of Reverse Diode 01/28/2008 Rev.1.00 Fig 6. Gate Threshold Voltage v.s. Junction Temperature 6 www.SiliconStandard.com SSM4501GSD P-Channel f=1.0MHz 12 1000 -VGS , Gate to Source Voltage (V) 10 I D =-5.0A V DS =-24V C iss 8 C (pF) C oss C rss 100 6 4 2 0 0 4 8 12 16 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty Factor = 0.5 100us 10 Normalized Thermal Response (Rthja) 0.2 1ms -ID (A) 10ms 1 0.1 0.1 0.05 0.02 100ms 1s 10s DC 0.01 0.01 PDM Single Pulse t T Duty Factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=90oC/W 0.1 T A =25 o C Single Pulse 0.01 0.1 1 10 0.001 100 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics VDS 90% VG QG -4.5V QGS QGD 10% VGS td(on) tr td(off)tf Charge Q Fig 11. Switching Time Waveform 01/28/2008 Rev.1.00 Fig 12. Gate Charge Waveform 7 www.SiliconStandard.com SSM4501GSD Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 01/28/2008 Rev.1.00 www.SiliconStandard.com 8 |
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